Formal Semantics And Proof Techniques For Optimizing Vhdl Models

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Formal Semantics And Proof Techniques For Optimizing Vhdl Models

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Formal Semantics And Proof Techniques For Optimizing Vhdl Models

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Formal Semantics And Proof Techniques For Optimizing Vhdl Models

Written Expressly For Hardware Designers, This Book Presents A Formal Model Of Vhdl Clearly Specifying Both The Static And Dynamic Semantics Of Vhdl. It Provides A Mathematical Framework For Representing Vhdl Constructs And Shows How Those Constructs Can Be Formally Manipulated To Reason About Vhdl.
  • Brand: Springer Nature B.V
  • Category: Computing & Internet
  • Format: Hardcover
  • Language: English
  • Publication Date: 1998-11-30
  • Publisher / Label: Springer Nature B.V
  • Author: Kothanda Umamageswaran
  • Number of Pages: 184
  • Fruugo ID: 556932932-1125171388
  • ISBN: 9780792383758
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