Verification By Error Modeling Using Testing Techniques In Hardware Verification

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Verification By Error Modeling Using Testing Techniques In Hardware Verification

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Verification By Error Modeling Using Testing Techniques In Hardware Verification

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Verification By Error Modeling Using Testing Techniques In Hardware Verification

This Book Presents The Basis For Reusing The Test Vector Generation And Simulation For The Purpose Of Implementation Verification, To Result In A Significant Timesaving. It Brings The Results In The Direction Of Merging Manufacturing Test Vector Generation And Verification.
  • Brand: Springer Nature B.V
  • Category: Computing & Internet
  • Format: Hardcover
  • Language: English
  • Publication Date: 2003-11-30
  • Publisher / Label: Springer Nature B.V
  • Author: Katarzyna Radecka
  • Number of Pages: 236
  • Fruugo ID: 557022043-1125287380
  • ISBN: 9781402076527
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